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FINAL
COM'L: -12/15/20
IND: -14/18/24
MACH215-12/15/20
High-Density EE CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
s s s s 44 Pins 32 Output Macrocells 32 Input Macrocells Product terms for: -- Individual flip-flop clock -- Individual asynchronous reset, preset -- Individual output enable 12 ns tPD Commercial 14.5 ns tPD Industrial 67 MHz fCNT s s s s s s
Lattice Semiconductor
38 Inputs with pull-up resistors 32 Outputs 64 Flip-flops For asynchronous and synchronous applications 4 "PAL22RA8" blocks with buried macrocells Pin-compatible with MACH110, MACH111, MACH210, and MACH211
s s
GENERAL DESCRIPTION
The MACH215 is a member of the high-performance EE CMOS MACH device family. This device has approximately three times the capability of the popular PAL20RA10 without loss of speed. This device is designed for use in asynchronous as well as synchronous applications. The MACH215 consists of four PAL blocks interconnected by a programmable switch matrix. The four PAL blocks are essentially "PAL22RA8" structures complete with product-term arrays and programmable macrocells, individual register control product terms, and input registers. The switch matrix connects the PAL blocks to each other and to all input pins, providing a high degree of connectivity between the fully-connected PAL blocks. This allows designs to be placed and routed efficiently. The MACH215 has two kinds of macrocell: output and input. The MACH215 output macrocell provides registered, latched, or combinatorial outputs with programmable polarity. If a registered configuration is chosen, the register can be configured as D-type or T-type to help reduce the number of product terms. The register type decision can be made by the designer or by the software. Each macrocell has its own dedicated clock, asynchronous reset, and asynchronous preset control. The polarity of the clock signal is programmable. All output macrocells can be connected to an I/O cell. The MACH215 has dedicated input macrocells which provide input registers or latches for synchronizing input signals and reducing setup time requirements.
Publication# 16751
Rev. E
Amendment/0
Issue Date: May 1995
BLOCK DIAGRAM
I/O0-I/O7 I/O8-I/O15 I0-I1, I3-I4
I/O Cells 8
8
I/O Cells 8 Output Macrocells
OE
8
Output Macrocells
OE
Input Macrocells
CLK
Input Macrocells
CLK
44x64 AND Logic Array and Logic Allocator 22
8
8
8
44x64 AND Logic Array and Logic Allocator 22
8
8
8 4
Switch Matrix
22 44x64 AND Logic Array and Logic Allocator
OE CLK
22 44x64 AND Logic Array and Logic Allocator
OE CLK
8
8
8
8
8
82
Output Macrocells
Input Macrocells
Output Macrocells 8
Input Macrocells
8 I/O Cells 8
I/O Cells
8
I/O24-I/O31
I/O16-I/O23
CLK0/I2 CLK1/I5
16751E-1
2
MACH215-12/15/20
CONNECTION DIAGRAM Top View PLCC
I/O31 I/O30 I/O2 I/O1 VCC I/O29 I/O28 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 I/O14 I/O15 GND I/O18 I/O19 VCC I/O12 I/O13 I/O16 I/O17 I/O20 I/O0 GND 2 I/O4 6 I/O5 I/O6 I/O7 I0 I1 GND CLK0/I2 I/O8 I/O9 I/O10 I/O11 7 8 9 10 11 12 13 14 15 16 17 I/O3 5
4
3
1 44 43 42 41 40 I/O27 I/O26 I/O25 I/O24 CLK1/I5 GND I4 I3 I/O23 I/O22 I/O21
16751E-2
Note: Pin-compatible with MACH110, MACH111, MACH210, and MACH211.
PIN DESIGNATIONS
CLK/I = GND = I = I/O = VCC Clock or Input Ground Input Input/Output
= Supply Voltage
MACH215-12/15/20
3
ORDERING INFORMATION Commercial Products
Programmable logic products for commercial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of:
MACH
215 -12
J
C
FAMILY TYPE MACH = Macro Array CMOS High-Speed DEVICE NUMBER 215 = 32 Asynchronous Output Macrocells, 44 Pins SPEED -12 = 12 ns tPD -15 = 15 ns tPD -20 = 20 ns tPD
OPTIONAL PROCESSING Blank = Standard Processing OPERATING CONDITIONS C = Commercial (0C to +70C) PACKAGE TYPE J = 44-Pin Plastic Leaded Chip Carrier (PL 044)
Valid Combinations MACH215-12 MACH215-15 MACH215-20 JC
Valid Combinations The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations.
4
MACH215-12/15/20 (Com'l)
ORDERING INFORMATION Industrial Products
Programmable logic products for industrial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of:
MACH
215 -14
J
I
FAMILY TYPE MACH = Macro Array CMOS High-Speed DEVICE NUMBER 215 = 32 Asynchronous Output Macrocells, 44 Pins SPEED -14 = 14.5 ns tPD -18 = 18 ns tPD -24 = 24 ns tPD
OPTIONAL PROCESSING Blank = Standard Processing OPERATING CONDITIONS I = Industrial (-40C to +85C) PACKAGE TYPE J = 44-Pin Plastic Leaded Chip Carrier (PL 044)
Valid Combinations MACH215-14 MACH215-18 MACH215-24 JI
Valid Combinations The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations.
MACH215-14/18/24 (Ind)
5
FUNCTIONAL DESCRIPTION
The MACH215 consists of four asynchronous PAL blocks connected by a switch matrix. There are 32 I/O pins and 4 dedicated input pins feeding the switch matrix. These signals are distributed to the four PAL blocks for efficient design implementation. There are also two additional global clock pins that can be used as dedicated inputs. This device provides two kinds of macrocell: output macrocells and input macrocells. This adds greater logic density without affecting the number of pins.
Table 1. Logic Allocation
Output Macrocell Available Clusters
The PAL Blocks
Each PAL block in the MACH215 (Figure 1) contains a 64-product-term array, a logic allocator, 8 output macrocells, 8 input macrocells, and 8 I/O cells. The switch matrix feeds each PAL block with 22 inputs. This makes the PAL block look effectively like an independent "PAL22RA8" with 8 input macrocells. All flip-flops within the device can operate independently.
M0 M1 M2 M3 M4 M5 M6 M7
C0, C1 C0, C1, C2 C1, C2, C3 C2, C3, C4 C3, C4, C5 C4, C5, C6 C5, C6, C7 C6, C7
The Macrocell
There are two types of macrocell in the MACH215: output macrocells and input macrocells. The output macrocell takes the logic of the device and provides it to I/O pins and/or provides feedback for additional logic generation. The input macrocell allows I/O pins to be configured as registered or latched inputs. The output macrocell (Figure 3) can generate registered or combinatorial outputs. In addition, a transparent-low latched configuration is provided. If used, the register can be configured as a T-type or a D-type flip-flop. Register and latch functionality is defined in Table 2. Programmable polarity and the T-type flip-flop both give the software a way to minimize the number of product terms needed. These choices can be made automatically by the software when it fits the design into the device. Table 2. Register/Latch Operation
Configuration D-Register D/T X 0 1 X 0 1 X 0 1 CLK/LE* 0, 1, () () () 0, 1, () () () 1 (0) 0 (1) 0 (1) Q+ Q 0 1 Q Q Q Q 0 1
The Switch Matrix
The MACH215 switch matrix is fed by the inputs and feedback signals from the PAL blocks. Each PAL block provides 16 internal feedback signals and 8 I/O feedback signals. The switch matrix distributes these signals back to the PAL blocks in an efficient manner that also provides for high performance. The design software automatically configures the switch matrix when fitting a design into the device.
The Product-term Array
The MACH215 product-term array consists of 32 product terms for logic use and 32 product terms for generating macrocell control signals.
The Logic Allocator
The logic allocator in the MACH215 (Figure 2) takes the 32 logic product terms and allocates them to the 16 macrocells as needed. Each macrocell can be driven by up to 12 product terms. The design software automatically configures the logic allocator when fitting the design into the device. Table 1 illustrates which product term clusters are available to each macrocell within a PAL block. Refer to Figure 1 for cluster and macrocell numbers.
T-Register
Latch
*Polarity of CLK/LE can be programmed.
6
MACH215-12/15/20
The output macrocell sends its output back to the switch matrix, via internal feedback, and to the I/O cell. The feedback is always available regardless of the configuration of the I/O cell. This allows for buried combinatorial or registered functions, freeing up the I/O pins for use as inputs if not needed as outputs. The basic output macrocell configurations are shown in Figure 4. The clock/latch-enable for each individual output macrocell can be driven by one of four signals. Two of the signals are provided by the global clock pin CLK0/LE0; either polarity may be chosen. The other two signals come from a product term provided for each output macrocell. Either polarity of the logic generated by the product term can be chosen. The global clock pin is also available as an input, although care must be taken when a signal acts as both clock and input to the same device. Each individual output macrocell also has a product term for asynchronous reset and a product term for asynchronous preset. This means that any register or latch may be reset or preset without affecting any other register or latch in the device. The functionality of the flip-flops with respect to initialization is illustrated in Table 3. Table 3. Asynchronous Reset/Preset Operation
AR 0 0 1 1 AP 0 1 0 1 CLK/LE X X X X Q+ See Table 12 1 0 0
The input macrocell (Figure 5) consists of a flip-flop that can be used to provide registered or latched inputs. The flip-flop can be clocked by either polarity of one of the two global clock/latch-enable pins. Reset or preset are not provided for these flip-flops. If combinatorial inputs are desired, this macrocell is not used, and the feedback from the I/O pin is used directly. Both the I/O pin feedback and the output of the input register or latch are always available to the switch matrix. Possible input macrocell configurations are shown in Figure 6.
The I/O Cell
The I/O cell (Figure 7) provides a three-state output buffer. The three-state control is provided by an individual product term for each I/O cell. Depending on the logic programmed onto this product term, the I/O pin can be configured as an output, an input, or a bidirectional pin. The feedback from the I/O pin is always available to the switch matrix, regardless of the state of the output buffer or the output macrocell.
MACH215-12/15/20
7
0
4
8
12
16
20
24
28
32
36
40
43
M0
2
Output Macro Cell
I/O Cell
I/O
2
Input Macro Cell
M1
2
Output Macro Cell
I/O Cell
I/O
2 0
Input Macro Cell
I/O Cell
I/O
C0
M2
2
Output Macro Cell
C1 Logic Allocator
2
Input Macro Cell
I/O Cell
I/O
C2 Switch Matrix
M3
2
Output Macro Cell
C3
2
Input Macro Cell
C4
M4
2
Output Macro Cell
I/O Cell
I/O
C5 C6 M5
2
Input Macro Cell
Output Macro Cell 2
I/O Cell
I/O
64 63
C7 M6
2
Input Macro Cell
I/O Cell Output Macro Cell 2
I/O
2
Input Macro Cell
M7
2
I/O Cell Output Macro Cell
I/O
2
Input Macro Cell
0
4
8
12
16
20
24
28
32
36
40
43 CLK0 CLK1
16 8
16751E-3
Figure 1. MACH215 PAL Block 8 MACH215-12/15/20
To n-1
From n-1
n
n
To Macrocell n
Product Term Cluster
To n+1
From n+1
Logic Allocator
16751E-4
Figure 2. Product Term Clusters and the Logic Allocator
Individual Asynchronous Preset Sum of Products from Logic Allocator CLK0 Individual Clock Individual Asynchronous Reset To Switch Matrix AP D/T/L Q
1 1 0 0 To I/O Cell
AR
16751E-5
Figure 3. Output Macrocell
MACH215-12/15/20
9
From Logic Allocator
n
To I/O Cell
From Logic Allocator
n
To I/O Cell
To Switch Matrix
To Switch Matrix
a. Combinatorial, Active High
Individual Preset From Logic Allocator CLK0 Individual Clock Individual Preset To Switch Matrix AR n D APQ To I/O Cell
b. Combinatorial, Active Low
Individual Preset From Logic Allocator CLK0 Individual Clock Individual Preset To Switch Matrix AR n D APQ To I/O Cell
c. D-type Register, Active High
Individual Preset From Logic Allocator CLK0 Individual Clock Individual Preset To Switch Matrix AR n T APQ To I/O Cell
d. D-type Register, Active Low
Individual Preset From Logic Allocator CLK0 Individual Clock Individual Preset To Switch Matrix AR n T APQ To I/O Cell
e. T-type Register, Active High
Individual Preset From Logic Allocator CLK0 Individual Clock Individual Preset To Switch Matrix G AR n L APQ To I/O Cell
f. T-type Register, Active Low
Individual Preset From Logic Allocator CLK0 Individual Clock Individual Preset To Switch Matrix G AR n L APQ To I/O Cell
g. Latch, Active High
h. Latch, Active Low
16751E-6
Figure 4. Output Macrocell Configurations
10
MACH215-12/15/20
From I/O Pin AP D/L Q CLK0 CLK1
To Switch Matrix
16751E-7
Figure 5. Input Macrocell
From I/O Cell
From I/O Cell
D CLK0 CLK1
Q CLK0 CLK1
L G
Q
To Switch Matrix
To Switch Matrix
a. Input Register
b. Input Latch
16751E-8
Figure 6. Input Macrocell Configurations
Individual Output Enable Product Term
From Output Macrocell
To Switch Matrix
To Input Macrocell
16751E-9
Figure 7. I/O Cell MACH215-12/15/20 11
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied . . . . . . . . . . . . . -55C to +125C Supply Voltage with Respect to Ground . . . . . . . . . . . . . -0.5 V to +7.0 V DC Input Voltage . . . . . . . . . . . . -0.5 V to VCC + 0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = 0C to +70C) . . . . . . . . . . . . . . . . . . . . 200 mA
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
OPERATING RANGES
Commercial (C) Devices Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . . +4.75 V to +5.25 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol VOH VOL VIH VIL IIH IIL IOZH IOZL ISC ICC Parameter Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current LOW Output Short-Circuit Current Supply Current (Typical) Test Conditions IOH = -3.2 mA, VCC = Min VIN = VIH or VIL IOL = 24 mA, VCC = Min VIN = VIH or VIL (Note 1) Guaranteed Input Logical HIGH Voltage for all Inputs (Note 2) Guaranteed Input Logical LOW Voltage for all Inputs (Note 2) VIN = 5.25 V, VCC = Max (Note 3) VIN = 0 V, VCC = Max (Note 3) VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 3) VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 3) VOUT = 0.5 V, VCC = Max (Note 4) VCC = 5 V, TA = 25C, f = 25 MHz (Note 5) -30 95 2.0 0.8 10 -100 10 -100 -160 Min 2.4 0.5 Typ Max Unit V V V V A A A A mA mA
Notes: Total IOL for one PAL block should not exceed 128 mA. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 5. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. 1. 2. 3. 4.
12
MACH215-12/15/20 (Com'l)
CAPACITANCE (Note 1)
Parameter Symbol CIN COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VIN = 2.0 V VOUT = 2.0 V VCC = 5.0 V, TA = 25C, f = 1 MHz Typ 6 8 Unit pF pF
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter Symbol Parameter Description tPD tSA tHA tCOA tWLA tWHA Maximum Frequency Using Product Term Clock (Note 1) External Feedback 1/(tSA + tCOA) Input, I/O, or Feedback to Combinatorial Output (Note 3) Setup Time from Input, I/O, or Feedback to Product Term Clock Register Data Hold Time Using Product Term Clock Product Term Clock to Output (Note 3) Product Term, Clock Width LOW HIGH D-type T-type D-type Internal Feedback (fCNTA) No Feedback 1/(tWLA + tWHA) D-type T-type T-type D-type T-type -12 Min Max 3 5 6 5 4 8 8 52.6 50 58.8 55.6 62.5 7 8 0 2 LOW Global Clock Width Maximum Frequency Using Global Clock (Note 1) HIGH D-type External Feedback 1/(tSS + tCOS) T-type D-type Internal Feedback (fCNTS) No Feedback tSLA tHLA tGOA tGWA tSLS tHLS tGOS tGWS 1/(tWLS + tWHS) T-type 6 6 66.7 62.5 83.3 76.9 83.3 5 5 16 8 7 0 10 6 6 9 10 0 11 8 8 14 12 -15 Min Max 3 6 7 6 4 9 9 41.7 40 45.5 43.5 55.6 10 11 0 2 6 6 50 47.6 66.6 62.5 83.3 6 6 19 12 13 0 12 10 18 15 -20 Min Max 3 8 9 8 4 12 12 33.3 32.2 35.7 34.5 41.7 13 14 0 2 8 8 40 38.5 50 47.6 62.5 8 8 22 12 22 20 Unit ns ns ns ns ns ns ns MHz MHz MHz MHz MHz ns ns ns ns ns ns MHz MHz MHz MHz MHz ns ns ns ns ns ns ns ns
fMAXA
tSS tHS tCOS tWLS tWHS
Setup Time from Input, I/O, or Feedback to Global Clock Register Data Hold Time Using Global Clock Global Clock to Output (Note 3)
fMAXS
Setup Time from Input, I/O, or Feedback to Product Term Gate Latch Data Hold Time Using Product Term Clock Product Term Gate to Output (Note 3) Product Term Gate Width LOW (for LOW transparent) or HIGH (for HIGH transparent) Setup Time from Input, I/O, or Feedback to Global Gate Latch Data Hold Time Using Global Gate Gate to Output (Note 3) Global Gate Width LOW (for LOW transparent) or HIGH (for HIGH transparent)
MACH215-12/15/20 (Com'l)
13
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) (continued)
Parameter Symbol Parameter Description tPDL tSIR tHIR tICO tICS Input, I/O, or Feedback to Output Through Transparent Input or Output Latch Input Register Setup Time Input Register Hold Time Input Register Clock to Combinatorial Output Input Register Clock to Output Register Setup D-type T-type tWICL tWICH fMAXIR tSIL tHIL tIGO tIGOL Maximum Input Register Frequency Input Latch Setup Time Input Latch Hold Time Input Latch Gate to Combinatorial Output Input Latch Gate to Output Through Transparent Output Latch Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Product Term Output Latch Gate Input Latch Gate to Output Latch Setup Using Product Term Output Latch Gate Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Global Output Latch Gate Input Latch Gate to Output Latch Setup Using Global Output Latch Gate Input Latch Gate Width LOW Input, I/O, or Feedback to Output Through Transparent Input and Output Latches Asynchronous Reset to Registered or Latched Output Asynchronous Reset Width (Note 1) Asynchronous Reset Recovery Time (Note 1) Asynchronous Preset to Registered or Latched Output Asynchronous Preset Width (Note 1) Asynchronous Preset Recovery Time (Note 1) Input, I/O, or Feedback to Output Enable (Note 3) Input, I/O, or Feedback to Output Disable (Note 3) 12 8 2 2 12 12 12 8 16 15 10 2 2 15 15 7 7 Input Register Clock Width LOW HIGH 1/(tWICL + tWICH) 12 13 6 6 83.3 2 2 17 19 8 8 2 2 15 15 16 6 6 83.3 2 2.5 20 22 10 10 -12 Min Max 14 2 2.5 18 20 21 8 8 62.5 2 3 25 27 -15 Min Max 17 2 3 23 -20 Min Max 22 Unit ns ns ns ns ns ns ns ns MHz ns ns ns ns ns ns
tSLLA tIGSA tSLLS tIGSS tWIGL tPDLL tAR tARW tARR tAP tAPW tAPR tEA tER
9 13 6 16 16
12 16 6 19 20 15 10 20
15 21 8 24 25 20 15 25 20 15 2 2 20 20
ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 2. See Switching Test Circuit for test conditions. Switching waveforms illustrate true clocks only. Switching waveforms can be used to illustrate both synchronous and asynchronous clock timing. For example, tSS is the tS parameter for synchronous clocks and tSA is the tS parameter for asynchronous clocks. 3. Parameters measured with 16 outputs switching.
14
MACH215-12/15/20 (Com'l)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied . . . . . . . . . . . . . -55C to +125C Supply Voltage with Respect to Ground . . . . . . . . . . . . . -0.5 V to +7.0 V DC Input Voltage . . . . . . . . . . . . -0.5 V to VCC + 0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = -40C to +85C) . . . . . . . . . . . . . . . . . . 200 mA
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
INDUSTRIAL OPERATING RANGES
Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . -40C to +85C Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . . . . +4.5 V to +5.5 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC CHARACTERISTICS over INDUSTRIAL operating ranges unless otherwise specified
Parameter Symbol VOH VOL VIH VIL IIH IIL IOZH IOZL ISC ICC Parameter Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Leakage Current Input LOW Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current LOW Output Short-Circuit Current Supply Current (Typical) Test Conditions IOH = -3.2 mA, VCC = Min VIN = VIH or VIL IOL = 24 mA, VCC = Min VIN = VIH or VIL (Note 1) Guaranteed Input Logical HIGH Voltage for all Inputs (Note 2) Guaranteed Input Logical LOW Voltage for all Inputs (Note 2) VIN = 5.25 V, VCC = Max (Note 3) VIN = 0 V, VCC = Max (Note 3) VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 3) VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.5 V, VCC = Max (Note 4) VCC = 5 V, TA = 25C, f = 25 MHz (Note 5) -30 95 2.0 0.8 10 -100 10 -100 -160 Min 2.4 0.5 Typ Max Unit V V V V A A A A mA mA
Notes: 1. Total IOL for one PAL block should not exceed 128 mA. 2. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. ). 3. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH 4. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 5. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset.
MACH215-14/18/24 (Ind)
15
CAPACITANCE (Note 1)
Parameter Symbol CIN COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VIN = 2.0 V VOUT = 2.0 V VCC = 5.0 V, TA = 25C, f = 1 MHz Typ 6 8 Unit pF pF
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2)
Parameter Symbol Parameter Description tPD tSA tHA tCOA tWLA tWHA Maximum Frequency Using Product Term Clock (Note 1) External Feedback 1/(tSA + tCOA ) Input, I/O, or Feedback to Combinatorial Output (Note 3) Setup Time from Input, I/O, or Feedback to Product Term Clock Register Data Hold Time Using Product Term Clock Product Term Clock to Output (Note 3) Product Term, Clock Width LOW HIGH D-type T-type D-type Internal Feedback (fCNTA ) No Feedback ) 1/(tWLA + tWHA D-type T-type T-type 10 10 42 40 47 44 50 8.5 10 0 10 LOW Global Clock Width Maximum Frequency Using Global Clock (Note 1) External Feedback 1/(tSS + tCOS ) HIGH D-type T-type D-type Internal Feedback (fCNTS ) No Feedback 1/(tWLS + tWHS ) T-type 7.5 7.5 53 50 66.5 61.5 66.5 6 6 19.5 10 8.5 0 12 7.5 7.5 11 12 0 13.5 10 7.5 7.5 40 38 53 50 66.5 7.5 7.5 23 14.5 16 0 14.5 D-type T-type 6 7.5 6 17 11 11 33 32 36 34.5 44.5 12 13.5 0 12 10 10 32 30.5 40 38 50 10 10 26.5 -14 Min Max 14.5 7.5 8.5 7.5 22 15 15 26.5 25.5 28.5 27.5 33 16 17 0 14.5 -18 Min Max 18 10 11 10 26.5 -24 Min Max 24 Unit ns ns ns ns ns ns ns MHz MHz MHz MHz MHz ns ns ns ns ns ns MHz MHz MHz MHz MHz ns ns ns ns ns ns ns ns
fMAXS
tSS tHS tCOS tWLS tWHS
Setup Time from Input, I/O, or Feedback to Global Clock Register Data Hold Time Using Global Clock Global Clock to Output (Note 3)
fMAXS
tSLA tHLA tGOA tGWA tSLS tHLS tGOS tGWS
Setup Time from Input, I/O, or Feedback to Product Term Gate Latch Data Hold Time Using Product Term Clock Product Term Gate to Output (Note 3) Product Term Gate Width LOW (for LOW transparent) or HIGH (for HIGH transparent) Setup Time from Input, I/O, or Feedback to Global Gate Latch Data Hold Time Using Global Gate Gate to Output (Note 3) Global Gate Width LOW (for LOW transparent) or HIGH (for HIGH transparent)
16
MACH215-14/18/24 (Ind)
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2) (continued)
Parameter Symbol Parameter Description tPDL tSIR tHIR tICO tICS Input, I/O, or Feedback to Output Through Transparent Input or Output Latch Input Register Setup Time Input Register Hold Time Input Register Clock to Combinatorial Output Input Register Clock to Output Register Setup D-type T-type tWICL tWICH fMAXIR tSIL tHIL tIGO tIGOL Input Register Clock Width Maximum Input Register Frequency Input Latch Setup Time Input Latch Hold Time Input Latch Gate to Combinatorial Output Input Latch Gate to Output Through Transparent Output Latch Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Product Term Output Latch Gate Input Latch Gate to Output Latch Setup Using Product Term Output Latch Gate Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Global Output Latch Gate Input Latch Gate to Output Latch Setup Using Global Output Latch Gate Input Latch Gate Width LOW Input, I/O, or Feedback to Output Through Transparent Input and Output Latches Asynchronous Reset to Registered or Latched Output Asynchronous Reset Width (Note 1) Asynchronous Reset Recovery Time (Note 1) Asynchronous Preset to Registered or Latched Output Asynchronous Preset Width (Note 1) Asynchronous Preset Recovery Time (Note 1) Input, I/O, or Feedback to Output Enable (Note 3) Input, I/O, or Feedback to Output Disable (Note 3) 14.5 10 14.5 14.5 14.5 10 19.5 18 12 18 18 8.5 8.5 11 16 7.5 19.5 19.5 18 12 24 24 18 24 24 LOW HIGH 1/(tWICL + tWICH ) 14.5 16 7.5 7.5 66.5 2.5 3 20.5 23 2.4 3 18 18 19.5 7.5 7.5 66.5 2.5 3.5 24 26.5 -14 Min Max 17 2.4 3.5 22 24 25.5 10 10 50 2.5 4 30 32.5 -18 Min Max 20.5 2.4 4 28 -24 Min Max 26.5 Unit ns ns ns ns ns ns ns ns MHz ns ns ns ns
tSLLA tIGSA tSLLS tIGSS tWIGL tPDLL tAR tARW tARR tAP tAPW tAPR tEA tER
10 10 14.5 19.5 7.5 23 24
12 12 18 25.5 10 29 30 24 18 30
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 2. See Switching Test Circuit for test conditions. Switching waveforms illustrate true clocks only. Switching waveforms can be used to illustrate both synchronous and asynchronous clock timing. For example, tSS is the tS parameter for synchronous clocks and tSA is the tS parameter for asynchronous clocks. 3. Parameters measured with 16 outputs switching.
MACH215-14/18/24 (Ind)
17
TYPICAL CURRENT VS. VOLTAGE (I-V) CHARACTERISTICS
VCC = 5.0 V, TA = 25C
IOL (mA) 80 60 40 20 VOL (V) -1.0 -0.8 -0.6 -0.4 -0.2 -20 -40 -60 -80 .2 .4 .6 .8 1.0
Output, LOW
IOH (mA) 25 1 -3 -2 -1 -25 -50 -75 -100 -125 -150 2 3 4 5 VOH (V)
16751E-10
Output, HIGH II (mA)
20 VI (V) -2 -1 -20 -40 -60 -80 -100 1 2 3 4 5
16751E-11
16751E-12
Input 18 MACH215-12/15/20
TYPICAL ICC CHARACTERISTICS
VCC = 5 V, TA = 25C
150
125 MACH215
100
ICC (mA)
75
50
25
0 0 10 20 30 40 50 60 70 80 90
16751E-13
Frequency (MHz)
The selected "typical" pattern is a 16-bit up/down counter. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. Maximum frequency shown uses internal feedback and a D-type register.
MACH215-12/15/20
19
TYPICAL THERMAL CHARACTERISTICS
Measured at 25C ambient. These parameters are not tested.
Parameter Symbol jc ja jma Parameter Description Thermal impedance, junction to case Thermal impedance, junction to ambient Thermal impedance, junction to ambient with air flow 200 lfpm air 400 lfpm air 600 lfpm air 800 lfpm air Typ PLCC 15 40 36 33 31 29 Units C/W C/W C/W C/W C/W C/W
Plastic jc Considerations
The data listed for plastic jc are for reference only and are not recommended for use in calculating junction temperatures. The heat-flow paths in plastic-encapsulated devices are complex, making the jc measurement relative to a specific location on the package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package. Furthermore, jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment.
20
MACH215-12/15/20
SWITCHING WAVEFORMS
Input, I/O, or Feedback
VT tPD
Combinatorial Output
VT
16751E-14
Combinatorial Output
Input, I/O, or Feedback tS Clock VT tCO Registered Output
VT tH
Input, I/O, or Feedback tSL Gate tPDL VT
16751E-15
VT tHL VT tGO VT
16751E-16
Latched Out
Registered Output
Latched Output (MACH 2, 3, and 4)
tWH Clock tWL
16751E-17
Gate tGWS
VT
16751E-18
Clock Width
Gate Width (MACH 2, 3, and 4)
Registered Input tSIR Input Register Clock Combinatorial Output VT tICO
VT tHIR
Registered Input Input Register Clock VT Output Register Clock
VT
VT
tICS
VT
16751E-20
16751E-19
Registered Input (MACH 2 and 4)
Input Register to Output Register Setup (MACH 2 and 4)
Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns-4 ns typical.
MACH215-12/15/20
21
SWITCHING WAVEFORMS
Latched In tSIL Gate
VT tHIL VT tIGO
Combinatorial Output
VT
16751E-21
Latched Input (MACH 2 and 4)
tPDLL Latched In Latched Out Input Latch Gate tIGOL VT
VT
tIGS Output Latch Gate
tSLL VT
16751E-22
Latched Input and Output (MACH 2, 3, and 4)
Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns-4 ns typical.
22
MACH215-12/15/20
SWITCHING WAVEFORMS
tWICH Clock tWICL
16751E-23
VT
Input Latch Gate tWIGL
VT
16751E-24
Input Register Clock Width (MACH 2 and 4)
Input Latch Gate Width (MACH 2 and 4)
tARW Input, I/O, or Feedback tAR Registered Output VT tARR Clock VT
16751E-25
tAPW VT Input, I/O, or Feedback tAP Registered Output VT tAPR Clock VT
16751E-26
VT
Asynchronous Reset
Asynchronous Preset
Input, I/O, or Feedback tER Outputs VOH - 0.5V VOL + 0.5V
VT tEA VT
16751E-27
Output Disable/Enable
Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns-4 ns typical.
MACH215-12/15/20
23
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS Must be Steady May Change from H to L May Change from L to H Don't Care, Any Change Permitted Does Not Apply OUTPUTS Will be Steady Will be Changing from H to L Will be Changing from L to H Changing, State Unknown Center Line is HighImpedance "Off" State
KS000010-PAL
SWITCHING TEST CIRCUIT
5V
S1
R1 Output R2 Test Point
CL
16751E-28
Commercial Specification tPD, tCO tEA tER S1 Closed Z H: Open Z L: Closed H Z: Open L Z: Closed 35 pF 300 5 pF 390 CL R1 R2
Measured Output Value 1.5 V 1.5 V H Z: VOH - 0.5 V L Z: VOL + 0.5 V
*Switching several outputs simultaneously should be avoided for accurate measurement.
24
MACH215-12/15/20
fMAX PARAMETERS
The parameter fMAX is the maximum clock rate at which the device is guaranteed to operate. Because the flexibility inherent in programmable logic devices offers a choice of clocked flip-flop designs, fMAX is specified for three types of synchronous designs. The first type of design is a state machine with feedback signals sent off-chip. This external feedback could go back to the device inputs, or to a second device in a multi-chip state machine. The slowest path defining the period is the sum of the clock-to-output time and the input setup time for the external signals (tS + tCO). The reciprocal, fMAX, is the maximum frequency with external feedback or in conjunction with an equivalent speed device. This fMAX is designated "fMAX external." The second type of design is a single-chip state machine with internal feedback only. In this case, flip-flop inputs are defined by the device inputs and flip-flop outputs. Under these conditions, the period is limited by the internal delay from the flip-flop outputs through the internal feedback and logic to the flip-flop inputs. This fMAX is designated "fMAX internal". A simple internal counter is a good example of this type of design; therefore, this parameter is sometimes called "fCNT." The third type of design is a simple data path application. In this case, input data is presented to the flip-flop and clocked through; no feedback is employed. Under these conditions, the period is limited by the sum of the data setup time and the data hold time (tS + tH). However, a lower limit for the period of each fMAX type is the minimum clock period (tWH + tWL). Usually, this minimum clock period determines the period for the third fMAX, designated "fMAX no feedback." For devices with input registers, one additional fMAX parameter is specified: fMAXIR. Because this involves no feedback, it is calculated the same way as fMAX no feedback. The minimum period will be limited either by the sum of the setup and hold times (tSIR + tHIR) or the sum of the clock widths (tWICL + tWICH). The clock widths are normally the limiting parameters, so that fMAXIR is specified as 1/(tWICL + tWICH). Note that if both input and output registers are use in the same path, the overall frequency will be limited by tICS. All frequencies except fMAX internal are calculated from other measured AC parameters. fMAX internal is measured directly.
CLK
CLK
(SECOND CHIP) LOGIC REGISTER LOGIC REGISTER
tS
t CO fMAX External; 1/(tS + tCO) CLK
tS
fMAX Internal (fCNT) CLK
LOGIC
REGISTER
REGISTER
LOGIC
tS
tSIR
tHIR fMAXIR ; 1/(tSIR + tHIR) or 1/(tWICL + tWICH)
16751E-29
fMAX No Feedback; 1/(tS + tH) or 1/(tWH + tWL)
MACH215-12/15/20
25
ENDURANCE CHARACTERISTICS
The MACH families are manufactured using our advanced Electrically Erasable process. This technology uses an EE cell to replace the fuse link used in bipolar parts. As a result, the device can be erased and reprogrammed, a feature which allows 100% testing at the factory.
Endurance Characteristics
Parameter Symbol Parameter Description Min 10 tDR N Min Pattern Data Retention Time Max Reprogramming Cycles 20 100 Units Years Years Cycles Test Conditions Max Storage Temperature Max Operating Temperature Normal Programming Conditions
26
MACH215-12/15/20
INPUT/OUTPUT EQUIVALENT SCHEMATICS
VCC
100 k 1 k VCC
ESD Protection
Input
VCC
VCC
100 k
1 k
Preload Circuitry
Feedback Input
16751E-30
I/O
MACH215-12/15/20
27
POWER-UP RESET
The MACH devices have been designed with the capability to reset during system power-up. Following powerup, all flip-flops will be reset to LOW. The output state will depend on the logic polarity. This feature provides extra flexibility to the designer and is especially valuable in simplifying state machine initialization. A timing diagram and parameter table are shown below. Due to the synchronous operation of the power-up reset and the
Parameter Symbol tPR tS tWL
wide range of ways VCC can rise to its steady state, two conditions are required to insure a valid power-up reset. These conditions are: 1. The VCC rise must be monotonic. 2. Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met.
Parameter Descriptions Power-Up Reset Time Input or Feedback Setup Time Clock Width LOW
Max 10 See Switching Characteristics
Unit s
VCC
Power 4V
tPR
Registered Output
tS
Clock
tWL
16751E-31
Power-Up Reset Waveform
28
MACH215-12/15/20
USING PRELOAD AND OBSERVABILITY
In order to be testable, a circuit must be both controllable and observable. To achieve this, the MACH devices incorporate register preload and observability. In preload mode, each flip-flop in the MACH device can be loaded from the I/O pins, in order to perform functional testing of complex state machines. Register preload makes it possible to run a series of tests from a known starting state, or to load illegal states and test for proper recovery. This ability to control the MACH device's internal state can shorten test sequences, since it is easier to reach the state of interest. The observability function makes it possible to see the internal state of the buried registers during test by overriding each register's output enable and activating the output buffer. The values stored in output and buried registers can then be observed on the I/O pins. Without this feature, a thorough functional test would be impossible for any designs with buried registers. While the implementation of the testability features is fairly straightforward, care must be taken in certain instances to insure valid testing. One case involves asynchronous reset and preset. If the MACH registers drive asynchronous reset or preset lines and are preloaded in such a way that reset or preset are asserted, the reset or preset may remove the preloaded data. This is illustrated in Figure 8. Care should be taken when planning functional tests, so that states that will cause unexpected resets and presets are not preloaded. Another case to be aware of arises in testing combinatorial logic. When an output is configured as combinatorial, the observability feature forces the output into registered mode. When this happens, all product terms are forced to zero, which eliminates all combinatorial data. For a straight combinatorial output, the correct value will be restored after the preload or observe function, and there will be no problem. If the function implements a combinatorial latch, however, it relies on feedback to hold the correct value, as shown in Figure 9. As this value may change during the preload or observe operation, you cannot count on the data being correct after the operation. To insure valid testing in these cases, outputs that are combinatorial latches should not be tested immediately following a preload or observe sequence, but should first be restored to a known state. All MACH 2 devices support both preload and observability. Contact individual programming vendors in order to verify programmer support.
Reset Figure 9. Combinatorial Latch
16751E-33
Preloaded HIGH D Q1
Q
AR
Preloaded HIGH D Q2
Q
AR
On Preload Mode Off
Q1
AR
Q2
Figure 8. Preload/Reset Conflict
16751E-32
Set
MACH215-12/15/20
29
PHYSICAL DIMENSIONS* PL 044 44-Pin Plastic Leaded Chip Carrier (measured in inches)
.685 .695
.650 .656
.042 .056
.062 .083
Pin 1 I.D. .685 .695 .650 .656 .500 .590 REF .630
.013 .021
.026 .032
.050 REF
.009 .015
.090 .120 .165 .180
SEATING PLANE
TOP VIEW
SIDE VIEW
16-038-SQ PL 044 DA78 6-28-94 ae
*For reference only. BSC is an ANSI standard for Basic Space Centering.
34
MACH215-12/15/20

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